R&D and test engineers who need to characterize serial interfaces of up to 28.4 Gb/s can use the M8061A 2:1 Multiplexer with optional de-emphasis to extend the rate of J-BERT N4903B pattern generator. For the most accurate receiver characterization results, the M8061A provides four calibrated de-emphasis taps, which can be extended to eight taps, built-in superposition of level interference and Clock/2 jitter injection. The M8061A is a 2-slot AXIe module that can be controlled via USB from J-BERT's user interface.
Application examples for M8061A:
Optical transceivers such as 100GBASE-LR4, -SR4 and -ER4, 32G Fibre Channel
SERDES and chip-to-chip interfaces, such as OIF CEI
Backplanes, cables, such as 100GBASE-KR4, -CR4
Next generation computer buses, such as PCI Express ? 4
Specifications
Output data rate = 300 Mb/s to 27.0 Gb/s (28.4 Gb/s when using J-BERT N4903B option D14)
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